European Patent Application 06291440 discloses a synchronization system for synchronizing modules in an integrated circuit including a so-called SKew Insensitive Link (SKIL) to implement a mesochronous mechanism (see also D. Mangano, et al.: “Skew Insensitive Physical Links for Network on Chip”, 1st International Conference on Nano-Networks (NANO-NET 2006), Lausanne, Switzerland, 14-16 Sep. 2006.
As is well known, the term “mesochronous” denotes a relationship between two signals such that their corresponding significant instants occur at the same average rate. A mesochronous network is thus a network where the clocks run with the same frequency but unknown relative phases.
The arrangement disclosed in European Patent Application 06291440 overcomes a number of disadvantages inherent in certain conventional techniques for mesochronous on-chip communication, which are based on implementations that are not standard (i.e. where standard-cell technologies cannot be used).
Exemplary of such conventional techniques are e.g.:                F. Mu, C. Svensson: “Self-Tested Self-Synchronization circuit for mesochronous clocking”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, February 2001, Vol. 48 No. 2, pp. 129-141;        B. Mesgarzadeh, C. Svensson, A. Alvandpour: “A new mesochronous clocking scheme for synchronization in SoC”, Proc. Of the ISCAS, 2002, pp. 605-609; or        E. C. Svensson: “Timing closure through globally synchronous, timing portioned design methodology”, 41st Conference on Design Automation Conference, (DAC'04), pp. 71-74.        
A number of patent documents disclose solutions that are not based on standard-cell technology or are not suitable for building full-duplex mesochronous links. For instance, US-A-2002/0073389 or US-A-2003/0053489 are exemplary of arrangements for supporting mesochronous on-chip communication.
Networks on Chip (NoCs) are usually designed according to a Globally Asynchronous Locally Synchronous (GALS) approach. Various approaches can be used to implement the GALS paradigm inside a NoC system.
A first solution is to build a clockless network that provides the transport service needed to interconnect the IP components running asynchronously, that is, with different clock signals locally generated. For instance, T. Bjerregaard and J. Sparsø. “Implementation of guaranteed services in the MANGO clockless network-on-chip”, IEE Proc.-Comput. Digit. Tech., Vol. 153, No. 4, July 2006 discloses an example of a clockless Network on Chip. Such an approach is quite attractive, but, again, is inevitably affected by some difficulties concerning the design flow: non-standard cells are used, design of self-timed circuits is not trivial and timing verification is not reliable. Another possible approach is to use synchronizers at clock domain boundaries between the NoC running at its own clock speed and the IPs components, as disclosed e.g. by A. Radulescu, et al.: “An efficient on-chip network interface offering guaranteed services shared-memory abstraction, and flexible network configuration” Proc. 2004 Design, Automation and Test in Europe Conf. (DATE 2004), (IEEE, 2004), pp. 4-17. This solution, breaking the clock tree, introduces some benefits, but does not mitigate the physical issues due to the wire-delay effects inside the network.